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ADE7880
Neutral Current Mismatch
In 3-phase systems, the neutral current is equal to the algebraic
sum of the phase currents
I N ( t ) = I A ( t ) + I B ( t ) + I C ( t )
If there is a mismatch between these two quantities, then a
tamper situation may have occurred in the system.
The ADE7880 computes the sum of the phase currents adding
the content of the IAWV, IBWV, and ICWV registers, and
storing the result into the ISUM 28-bit signed register: I SUM (t) =
I A (t) + I B (t) + I C (t). ISUM is computed every 125 μs (8 kHz
frequency), the rate at which the current samples are available,
and Bit 17 (DREADY) in the STATUS0 register is used to signal
Processor section for more details on Bit DREADY.
To recover I SUM (t) value from the ISUM register, use the
following equation:
Data Sheet
ISUMLVL, the positive threshold used in the process, is a 24-bit
signed register. Because it is used in a comparison with an
absolute value, always set ISUMLVL as a positive number,
somewhere between 0x00000 and 0x7FFFFF. ISUMLVL uses
the same scale of the current ADCs outputs, so writing
+5,326,737 (0x514791) to the ISUMLVL register puts the
ADC section for details. Writing 0x000000, the default value, or
a negative value, signifies the MISMTCH event is always triggered.
The right value for the application should be written into the
ISUMLVL register after power-up or after a hardware/software
reset to avoid continuously triggering MISMTCH events.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. As presented in Figure 61, ISUM,
the 28-bit signed register, is accessed as a 32-bit register with the
four most significant bits padded with 0s.
I SUM ( t ) =
ISUM[27:0]
ADC MAX
× I FS
31
0000
28 27
28-BIT SIGNED NUMBER
0
where:
ADC MAX = 5,928,256, the ADC output when the input is at full
scale.
I FS is the full-scale ADC phase current.
Note that the ADE7880 also computes the rms of ISUM and
stores it into NIRMS register when Bit 2 (INSEL) in CONFIG3
register is set to 1 (see Current RMS Calculation section for
details).
The ADE7880 computes the difference between the absolute
values of ISUM and the neutral current from the INWV
register, take its absolute value and compare it against the
ISUMLVL threshold.
If
BIT 27 IS A SIGN BIT
Figure 61. The ISUM[27:0] Register is Transmitted As a 32-Bit Word
Similar to the registers presented in Figure 43, the ISUMLVL
register is accessed as a 32-bit register with four most significant
bits padded with 0s and sign extended to 28 bits.
PHASE COMPENSATION
ADC sections, the data path for both current and voltages is the
same. The phase error between current and voltage signals
introduced by the ADE7880 is negligible. However, the ADE7880
must work with transducers that may have inherent phase
errors. For example, a current transformer (CT) with a phase
error of 0.1° to 3° is not uncommon. These phase errors can
ISUM ? INWV ≤ ISUMLVL
,
vary from part to part, and they must be corrected to perform
accurate power calculations.
then it is assumed that the neutral current is equal to the sum
of the phase currents, and the system functions correctly.
If
ISUM ? INWV > ISUMLVL
,
then a tamper situation may have occurred, and Bit 20
(MISMTCH) in the STATUS1 register is set to 1. An interrupt
attached to the flag can be enabled by setting Bit 20
(MISMTCH) in the MASK1 register. If enabled, the IRQ1 pin is
set low when Status Bit MISMTCH is set to 1. The status bit is
cleared and the IRQ1 pin is set back to high by writing to the
STATUS1 register with Bit 20 (MISMTCH) set to 1.
If ISUM ? INWV ≤ ISUMLVL , then MISMTCH = 0
If ISUM ? INWV > ISUMLVL , then MISMTCH = 1
The errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE7880 provides a
means of digitally calibrating these small phase errors. The
ADE7880 allows a small time delay or time advance to be
introduced into the signal processing chain to compensate for
the small phase errors.
The phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) are 10-bit registers that can vary the time advance
in the voltage channel signal path from ?374.0 μs to +61.5 μs.
Negative values written to the PHCAL registers represent a time
advance whereas positive values represent a time delay. One LSB
is equivalent to 0.976 μs of time delay or time advance (clock
rate of 1.024 MHz). With a line frequency of 60 Hz, this gives
a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the
fundamental. This corresponds to a total correction range of
?8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is
Rev. A | Page 36 of 104
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